Dielectric energy converter

ABSTRACT

A circuit design for efficiently transferring significant levels of electrical power with non-inductive circuit elements. Power is transferred using synchronously-switched capacitive elements in such a way that both discharge from the power source and charge transferred to a load (and/or back to the power supply) are supplied as low duration, high-intensity current pulses. The synchronous power transfer alternates between connecting capacitive charge storage elements in parallel and in series so that both step-up and step-down topologies may be readily realized.

CROSS REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit of U.S. Provisional Application No.62/296,725, filed on Feb. 18, 2016, which is incorporated herein byreference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is directed generally to the field of electricalpower transfer and management.

2. Description of the Related Art

There are a multitude of well-known techniques for conditioning powerfrom an electrical source to most efficiently supply that power to aload. These are typically based on manipulating current and voltage tomatch load requirements. When the supply is in the form of alternatingcurrent (“AC”), a transformer might be used to transform a high voltageand low current into a lower voltage and higher current, or theconverse. When the power source is in the form of direct current (“DC”),a preferred contemporary methodology converts the DC power to ahigh-frequency pulsed form, manipulates the voltage and currentrelationship using magnetic elements such as transformers or inductors,then converts the pulsed form back to direct current in a form moresuitable to the application. The general terminology used to describethis type of circuit topology is switched-voltage conversion

Another variation on the switched-voltage conversion methodology is touse capacitors to store energy, and electronic switches to transformthat energy from one level of voltage and current to another. Suchso-called switched-capacitor arrays are routinely used in low currentcircuit applications to multiply operating voltages and thereby producethe appropriate voltage to power a given circuit, but are seldom if everseen in higher power applications.

Magnetic power conversion circuits are often complex, inefficient, andcostly, especially when voltages need to be boosted from lower to higherlevels. Switched-capacitor networks can do a good job of doubling ortripling input voltage, but have traditionally been limited to very lowpower applications due to limitations imposed by the commonly acceptedswitched-capacitor converter topologies.

Therefore, a need exists for devices configured to condition powerreceived from a power source and supply the conditioned power back tothe power source and/or to a load. Devices that avoid inductive elementsand/or magnetic elements and/or are suitable for higher powerapplications are particular desirable. The present application providesthese and other advantages as will be apparent from the followingdetailed description and accompanying figures.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

FIG. 1 is a circuit diagram of a first embodiment of a circuit that maybe used to implement a dielectric energy converter.

FIG. 2 illustrates a phase relationship between a pair of clock signals.

FIG. 3A is a circuit diagram of an analog clock generator circuit.

FIG. 3B is a circuit diagram of a digital clock generator circuit.

FIG. 3C is a circuit diagram of an exemplary isolated level shiftinggate driver or level shifting network.

FIG. 4 is a circuit diagram of a second embodiment of a circuitincluding an input switch that isolates a power source from theremainder of the circuit.

FIG. 5 is a circuit diagram of a third embodiment of a circuit includingan output switch that isolates a load from the remainder of the circuit.

FIG. 6 is a circuit diagram of a fourth embodiment of a circuit thatincludes the input switch that isolates the power source from theremainder of the circuit and the output switch that isolates the loadfrom the remainder of the circuit.

FIG. 7 is a circuit diagram of a fifth embodiment of a circuitconfigured to perform a Step-Down operation.

FIG. 8 is a circuit diagram of a sixth embodiment of a circuitconfigured for a battery tender application.

FIG. 9 is a circuit diagram of cascaded circuit modules configured toperform a Step-Up operation.

FIG. 10 is a circuit diagram of cascaded circuit modules configured toperform a Step-Down operation.

FIG. 11 is a block diagram illustrating an apparatus that may be used toimplement a dielectric energy converter.

Like reference numerals have been used in the figures to identify likecomponents.

DETAILED DESCRIPTION OF THE INVENTION

Overview

FIG. 11 illustrates an apparatus 100 that includes a circuit 102, one ormore drive circuits 104, and one or more pulse generating circuits 106.The apparatus 100 may be characterized as being a dielectric energyconverter. The circuit 102 has a unique switched-capacitor voltageconverter topology that is capable of transforming significant levels ofpower received from a power source 110 to levels appropriate to besupplied to a wide range of loads (e.g., a load 120). For example, thepower source 110 may be implemented as a power supply circuit configuredto provide a range of input voltages (e.g., about 12 Volts to about 60Volts) and/or supply a range of output voltages (e.g., about 12 Volts toabout 60 Volts) to the load 120 and/or back to the power source 110.When the power source 110 is implemented as a battery 130 (see FIG. 8),this topology takes advantage of its intrinsic pulsed nature to provideimproved battery performance and life. The power source 110 may beconnected to the drive circuit(s) 104 (e.g., via a conductor 108A)and/or the pulse generating circuit(s) 106 (e.g., via a conductor 108B)and may provide power thereto.

As will be explained in detail below, the circuit 102 includes aplurality of energy storage devices 140 (e.g., capacitors C1 and C2illustrated in FIG. 1) connected by conductors (e.g., wires, circuittraces, and the like) to a plurality of switching devices 150. Each ofthe energy storage devices 140 may be implemented as a capacitiveelement, a battery, and the like.

The switching devices 150 include one or more first switching devices152 (e.g., switching elements Q1 and Q3 illustrated in FIG. 1) and oneor more second switching devices 154 (e.g., a switching element Q2illustrated in FIG. 1) arranged in a switching array 156 with the energystorage devices 140. By way of non-limiting examples, one or more of theswitching devices 150 may each be implemented as a bipolar transistor, ametal-oxide-semiconductor field-effect transistor (“MOSFET”), an NChannel power MOSFET, a power MOSFET, a diode (e.g., a Shottky diode),and the like. As will be explained in detail below, when the circuit 102is operating, the one or more first switching devices 152 are conducting(or ‘On’) when the one or more second switching devices 154 are notconducting (or ‘Off’). Similarly, when the one or more second switchingdevices 154 are ‘On,’ the one or more first switching devices 152 are‘Off.’

The circuit 102 also includes contacts 160 and 162 configured to beconnected to the power source 110. Optionally, the circuit 102 mayinclude contacts 164 and 166 configured to be connected to the optionalload 120. As will be explained below, the circuit 102 may include aswitching element Q4 (see FIGS. 4 and 6) positioned between the contact160 and the remainder of the circuit 102 to isolate the power source 110from the circuit 102. Similarly, the circuit 102 may include a switchingelement Q5 (see FIGS. 5 and 6) positioned between the contact 164 andthe remainder of the circuit 102 to isolate the load 120 from thecircuit 102 and/or the power source 110.

The circuit 102 receives first and second trigger signals 170 and 172from the drive circuit(s) 104. By way of a non-limiting example, thedrive circuit(s) 104 may be implemented as a pair of level shiftingnetworks each like a level shifting network 290 illustrated in FIG. 3C.Returning to FIG. 11, the first trigger signal 170 is received (e.g.,via one or more conductors) by the one or more first switching devices152 and indicates whether the one or more first switching devices 152are ‘On’ or ‘Off.’ Similarly, the second trigger signal 172 is received(e.g., via one or more conductors) by the one or more second switchingdevices 154 and indicates whether the one or more second switchingdevices 154 are “On” or “Off.”

Each of the first and second trigger signals 170 and 172 may beimplemented as a square wave, a sinusoid, and the like. In theembodiment illustrated, each of the first and second trigger signals 170and 172 is a square wave with a series of pulses having a pulse widthand a frequency. The pulse widths of the first and second triggersignals 170 and 172 are substantially equal to one another. Similarly,the frequencies of the first and second trigger signals 170 and 172 aresubstantially equal to one another.

The first and second trigger signals 170 and 172 are generated based onthe first and second clock signals 180 and 182 received from the pulsegenerating circuit(s) 106 (e.g., an analog clock generator circuit 270illustrated in FIG. 3A, a digital clock generator circuit 280illustrated in FIG. 3B, and the like). In the embodiment illustrated,the first trigger signal 170 is created from the first clock signal 180and the second trigger signal 172 is created from the second clocksignal 182. Thus, by modifying characteristics of the first and secondclock signals 180 and 182, corresponding characteristics of the firstand second trigger signals 170 and 172 may be modified. Each of thefirst and second clock signals 180 and 182 may be implemented as asquare wave, a sinusoid, and the like. In the embodiment illustrated,each of the first and second clock signals 180 and 182 is a square wavewith a series of pulses having a pulse width and a frequency. The pulsewidths of the first and second clock signals 180 and 182 aresubstantially equal to one another. Similarly, the frequencies of thefirst and second clock signals 180 and 182 are substantially equal toone another. As shown in FIG. 2, the first and second clock signals 180and 182 are synchronized and have phases (labeled “Phase A” and “PhaseB,” respectively) that are offset from one another by 180 degrees.Similarly, referring to FIG. 11, the first and second trigger signals170 and 172 have phases that are offset from one another by 180 degrees.

The topology is configured to efficiently transfer significant amountsof energy (or electrical current) to the optional load 120 (and/or backto the power source 110), while offering great flexibility with regardto the transfer function itself. The pulse generating circuit(s) 106 maybe implemented as a two-phase push-pull clock generator (e.g., thedigital clock generator circuit 280 illustrated in FIG. 3B) thatcontrols the transfer function in an alternating fashion such that theenergy storage devices 140 (e.g., capacitors C1 and C2 illustrated inFIG. 1) are synchronously connected in series or parallel to the powersource 110 and, optionally, to the load 120. Output power level is madecontinuously variable by varying the frequency and the pulse width ofthe first and second clock signals 180 and 182. By way of a non-limitingexample, referring to FIG. 3B, the digital clock generator circuit 280may include encoders 282 and 284 for controlling the frequency and thepulse width, respectively. Referring to FIG. 11, the frequency and/orthe pulse width of the first and second clock signals 180 and 182 may becontrolled by a digital communications protocol, such as RS-232 serial,Bluetooth protocol, and the like. Alternatively, the pulse generatingcircuit(s) 106 may be configured to provide the first and second clocksignals 180 and 182 having a fixed frequency and a fixed pulse width.

By way of non-limiting examples, the circuit 102 may be implemented as aboost circuit (e.g., see FIGS. 1, 4-6, and 9) or a buck circuit (e.g.,see FIGS. 7 and 10) with neither implementation including or requiringany magnetic circuitry elements.

Applications of this topology include battery charging and dischargemanagement, battery conditioning, motor control, voltage regulation, andlighting control.

An inherent aspect of this topology is that distribution of energy isdone in a pulsed manner. Batteries in particular show improvements inboth charge and discharge performance when energy is transferred via atrain of high current pulses of very short duration.

First Embodiment

FIG. 1 is a circuit diagram of a first embodiment of a circuit 200 thatmay be used to implement the circuit 102 (see FIG. 11). In thisembodiment, the one or more first switching devices 152 (see FIG. 11)are implemented as the switching elements Q1 and Q3, and the one or moresecond switching devices 154 (see FIG. 11) are implemented as theswitching element Q2. Thus, the switching array 156 (see FIG. 11)includes the switching elements Q1-Q3. The energy storage devices 140are implemented as the capacitors C1 and C2. Together, the switchingelements Q1-Q3 and the capacitors C1 and C2 may be characterized asforming a synchronous bi-phase switched-capacitor circuit array 210.

The power source 110 (see FIG. 11) may be connected to the circuit 200at the contacts 160 and 162 (also labeled “INPUT_POSITIVE” and“INPUT_COMMON,” respectively, in FIG. 1). The load 120 (see FIG. 11) maybe connected to the circuit 200 at the contacts 164 and 166 (alsolabeled “OUTPUT_POSITIVE” and “OUTPUT_COMMON,” respectively, in FIG. 1).Thus, in FIG. 1, the power source 110 (see FIG. 11) and the load 120(see FIG. 11) are directly connected to the circuit 200. This results inthe load 120 receiving a composite waveform that includes both powerdelivered directly from the power source 110 and power supplied by thecapacitors C1 and C2 through at least a portion of the circuit 200.

In the circuit 200, the contact 160 is connected by a conductor T1 to anode N1. The node N1 is connected to the capacitor C1 and the switchingelement Q1 by conductors T2 and T3, respectively. The capacitor C1 isalso connected to a node N2 by a conductor T4. The contact 162 is alsoconnected to the node N2 by a conductor T5. The node N2 is connected toa node N3 by a conductor T6. The node N3 is connected to a node N4 by aconductor T7. The contact 164 is connected to the node N4 by a conductorT8. The switching element Q1 is connected to a node N5 by a conductorT9. The node N5 is connected to the switching element Q2 by a conductorT10. The switching element Q2 is connected to the node N3 by a conductorT11. The node N5 is connected to the capacitor C2 by a conductor T12.The capacitor C2 is connected to a node N6 by a conductor T13. Thecontact 166 is connected to the node N6 by a conductor T14. The node N6is connected to the switching element Q3 by a conductor T15. Theswitching element Q3 is connected to the node N4 by a conductor T16.Thus, in the circuit 200, the power source 110 (see FIG. 11) isconnectable across the capacitor C1 and the load 120 (see FIG. 11) isconnectable across the switching element Q3.

As will be described below, how and where the contacts 160-166 connectto the remainder of the circuit 200 may be modified. Therefore, thecircuit 200 may be characterized as including a core circuit module 220that excludes the contacts 160-166 and any conductors (e.g., conductorsT1, T5, T8, and T14) that connect the contacts 160-166 to the remainderof the circuit 200.

Referring to FIG. 1, the circuit 200 alternates between connectingcapacitors C1 and C2 in parallel (referred to as a “parallel phase” or a“parallel state”) and in series (referred to as a “serial phase” or a“serial state”). In this embodiment, the capacitors C1 and C2 chargeduring the parallel state and discharge during the serial state.

The switching elements Q1 and Q3 are driven by the first trigger signal170 (see FIG. 11), which is labeled by its “Phase A” in FIG. 1. Theswitching element Q2 is driven by the second trigger signal 172 (seeFIG. 11), which is labeled by its “Phase B” in FIG. 1. The switchingelements Q1 and Q3 are “On” when an amplitude of the first triggersignal 170 (see FIG. 11) exceeds a first ‘On’ threshold. When “On,” theswitching elements Q1 and Q3 connect the capacitors C1 and C2 inparallel and the circuit 200 operates in the parallel state. Theswitching element Q2 is “On” when an amplitude of the second triggersignal 172 (see FIG. 11) exceeds a second ‘On’ threshold. When “On,” theswitching element Q2 connects the capacitors C1 and C2 in series and thecircuit 200 operates in the serial state.

Referring to FIG. 11, the one or more pulse generating circuits 106control a switch rate and a pulse width of each of the first and secondtrigger signals 170 and 172. By appropriately controlling the switchrate and the pulse width of the switching pulses of the first and secondtrigger signals 170 and 172, extremely high transfer efficiencies may beachieved, and significant power transfer levels are possible.Additionally, both the switching rate and the pulse width may be variedto regulate the power transfer ratio as desired. In practice, switchingrates in the range from 100 Hz to 100 kHz have been shown to producegood coupling efficiency.

Referring to FIG. 1, it will be understood by those of ordinary skill inthe art that the switching elements Q1-Q3 each require a separate,isolated gate drive signal (e.g., generated from the first and secondclock signals 180 and 182 illustrated in FIG. 11). By way of anon-limiting example, one or more of the switching elements Q1-Q3 mayeach be implemented as an N Channel power MOSFET. In such embodiments,the switching elements Q1-Q3 each have a gate. The first trigger signal170 delivered to the gates of the switching elements Q1 and Q3 must havea sufficient maximum amplitude (e.g., 5 volts) to exceed the first ‘On’threshold. Similarly, the second trigger signal 172 delivered to thegate of the switching element Q2 must have a sufficient maximumamplitude (e.g., 5 volts) to exceed the second ‘On’ threshold. FIG. 3Cis a circuit diagram of the level shifting network 290 configured togenerate the first and second trigger signals 170 and 172). Referring toFIG. 11, the drive circuit(s) 104 may include a separate circuit likethe level shifting network 290 (see FIG. 3C) for each of the first andsecond trigger signals 170 and 172. As shown in FIG. 3C, the levelshifting network 290 may include a DC-DC-converter U4 (e.g., implementedas a 12V-12V isolated DC-DC converter, such as an NKE1212) connected toan opto isolator U5 (e.g., implemented as optocoupler, such as aTLP152).

Referring to FIG. 11, the pulse generating circuit(s) 106 may becharacterized as being control circuitry. By way of non-limitingexample, the power source 110 may be implemented as a power supplycircuit configured to provide a wide range of input or output voltages(e.g., about 12 Volts to about 60 Volts), while holding the controlcircuitry at a constant voltage. The drive circuit(s) 104 isolate thefirst and second trigger signals 170 and 172 from the control circuitry.While powering the circuit 200, the power supply 110 may provide aconstant voltage (e.g., via the conductor 108B) to the controlcircuitry.

FIG. 2 illustrates examples of typical clock signals that may be used toimplement the first and second clock signals 180 and 182. In thesimplest case, the first and second clock signals 180 and 182 are each a50 percent duty cycle square wave and are offset from one another by 180degrees of phase. In some embodiments, the pulse generating circuit(s)106 allow adjustment of the pulse width.

By way of a non-limiting example, the first and second clock signals 180and 182 may be generated by the analog clock generator circuit 270illustrated in FIG. 3A or the digital clock generator circuit 280illustrated in FIG. 3B. Referring to FIG. 3A, the analog clock generatorcircuit 270 may be characterized as being an analog biphase clockgenerator. In the analog clock generator circuit 270, an inverter U1(e.g., a Schmitt inverter having a part number TC7S14), a capacitor C3,and a variable resistor R1 (e.g., a potentiometer) form a conventionalsquare-wave oscillator. The values of both the capacitor C3 and thevariable resistor R1 may be varied or modified to change the operatingfrequency. In the embodiment illustrated, the variable resistor R1facilitates continuous adjustment of oscillator frequency. The analogclock generator circuit 270 includes a microcontroller U2 that generatesa biphase drive signal. The inverter U1 drives the microcontroller U2.The microcontroller U2, in this example a PIC12F1822 eight-bit device,is programmed to provide two square wave outputs of opposing phase,namely, the first and second clock signals 180 and 182 (see FIG. 11). Aswith most drivers typical of this sort, a dead zone is programmed sothat the two gate drive phases can never be in the ‘high’ state at thesame time. The microcontroller U2 may be characterized as being adigital single-to-bi-phase converter that generates the first and secondclock signals 180 and 182 (see FIG. 11), with each of the first andsecond clock signals 180 and 182 (see FIG. 11) having a constant 50percent duty cycle. The first and second clock signals 180 and 182 (seeFIG. 11) include first and second timing pulses, respectively, that mayeach be varied continuously over a range of approximately 100 Hz toapproximately 100 kHz. The first and second clock signals 180 and 182(see FIG. 11) may have first and second phases, respectively, offset byabout 180 degrees.

Referring to FIG. 3B, the digital clock generator circuit 280 may becharacterized as being a digital biphase clock generator. In thisexample a microcontroller U3 with a hardware-based complementary outputgenerator, such as a PIC16F1617 part, generates a master clock frequencyas well as generating a push-pull biphase pair of output signals,namely, the first and second clock signals 180 and 182 (see FIG. 11).The microcontroller U3 may be characterized as being a digital timingcircuit that generates the first and second clock signals 180 and 182(see FIG. 11) in a push-pull timing configuration in which the firstpulse width is equal to the second pulse width. The microcontroller U3may be configured to vary an operating frequency of the digital clockgenerator circuit 280 over a range of approximately 100 Hz toapproximately 500 kHz, and to vary the first and second pulse widthsover a duty cycle having a range from approximately 1 percent toapproximately 100 percent.

As mentioned above, the frequency and/or the pulse width of the firstand second clock signals 180 and 182 (see FIGS. 2 and 11) may becontrolled by a digital communications protocol (e.g., RS-232 serial,Bluetooth protocol, and the like). In such embodiments, the digitalclock generator circuit 280 may include an optional communications linkU6 (e.g., an RS-232 communications link) connected to themicrocontroller U2. The communications link U6 may include acommunication connector 286 configured to be connected to anothercomponent and to receive digital communications therefrom. Thecommunications link U6 communicates those digital communications to themicrocontroller U2, which is configured to adjust the operatingfrequency and/or the pulse widths of the first and second clock signals180 and 182 (see FIGS. 2 and 11) based at least in part on the digitalcommunications. Thus, the digital communications protocol may be used tovary the operating frequency of the digital clock generator circuit 280as well as the first and second pulse widths of the first and secondclock signals 180 and 182, respectively (see FIG. 11). By way ofnon-limiting example, the communication connector 286 may be connectedto an external microprocessor, a Personal Computer communications bus,or the like.

Referring to FIG. 11, there are a number of methodologies, included aspart of this application, for interfacing the power source 110 and theload 120 with the core circuit module 220 (see FIG. 1). Each methodologyhas beneficial aspects appropriate to specific applications, as noted inthe following descriptions of second, third, and fourth embodiments.

Second Embodiment

FIG. 4 is a circuit diagram of the second embodiment of a circuit 300that may be used to implement the circuit 102 (see FIG. 11). In thecircuit 300, the power source 110 (see FIG. 11) is connected to the corecircuit module 220 through a switching element Q4. The power source 110(see FIG. 11) is connected to the contact 160, which is connected by aconductor T1-A to the switching element Q4. The switching element Q4 isconnected by a conductor T1-B to the node N1. As in the circuit 200 (seeFIG. 1), the contact 162 is connected to the node N2 by the conductorT5. The remainder of the circuit 300 is substantially identical to thecircuit 200 (see FIG. 1).

By way of a non-limiting example, the switching element Q4 may beimplemented as a power MOSFET or the equivalent. In this embodiment, thepower source 110 (see FIG. 11) is isolated from the remainder of thecircuit 300 (e.g., the core circuit module 220) by the switching elementQ4.

The switching element Q4 receives and is controlled by the first triggersignal 170 (see FIG. 11), which is labeled by its “Phase A” in FIG. 4.Thus, the first trigger signal 170 controls, in a synchronous fashion,the switching elements Q1 and Q3 that when ‘On,’ connect the capacitorsC1 and C2 in parallel, and the switching element Q4 that when ‘On’connects the power source 110 (see FIG. 11) to the circuit 300. When theswitching element Q4 is ‘Off,’ the power source 110 (see FIG. 11) isdisconnected from the remainder of the circuit 300. In this embodiment,the power source 110 is connected to the core circuit module 220 duringthe parallel phase of clocked operation, and disconnected during theserial phase of clocked operation. The load 120 is always connected tothe core circuit module 220, and thus receives current from thecapacitors C1 and C2, whether the capacitors C1 and C2 are connected inseries or parallel.

Third Embodiment

FIG. 5 is a circuit diagram of the third embodiment of a circuit 400that may be used to implement the circuit 102 (see FIG. 11). In thecircuit 400, the power source 110 (see FIG. 11) is connected directly tothe core circuit module 220, and the load 120 (see FIG. 11) is connectedthrough a switching element Q5. The power source 110 (see FIG. 11) isconnected to the contact 160, which is connected by the conductor T1-Ato a node N7. The node N7 is connected by the conductor T1-B to the nodeN1. The load 120 (see FIG. 11) is connected to the contact 164, which isconnected by a conductor T8-A to the switching element Q5. The switchingelement Q5 is connected by a conductor T8-B to the node N7. Theremainder of the circuit 400 is substantially identical to the circuit200 (see FIG. 1).

In this embodiment, the load 120 (see FIG. 11) is isolated from both theremainder of the circuit 400 (e.g., the core circuit module 220) and thepower source 110 by the switching element Q5. The switching element Q5receives and is controlled by the second trigger signal 172 (see FIG.11), which is labeled by its “Phase B” in FIG. 5. Thus, the secondtrigger signal 172 controls, in a synchronous fashion, the switchingelements Q2 and Q5.

In this embodiment, the power source 110 (see FIG. 11) is alwaysconnected to the core circuit module 220, and the load 120 (see FIG. 11)is connected to the core circuit module 220 during the serial phase ofclocked operation (during which the capacitors C1 and C2 are connectedin series), and disconnected during the parallel phase (during which thecapacitors C1 and C2 are connected in parallel) of clocked operation. Inthis embodiment, only the doubled supply voltage is delivered in pulseform to the load 120 (see FIG. 11).

Fourth Embodiment

FIG. 6 is a circuit diagram of the fourth embodiment of a circuit 500that may be used to implement the circuit 102 (see FIG. 11). In thecircuit 500, the power source 110 (see FIG. 11) is connected to the corecircuit module 220 through the switching element Q4 and the load 120(see FIG. 11) is connected to the core circuit module 220 through theswitching element Q5. The power source 110 (see FIG. 11) is connected tothe contact 160, which is connected by the conductor T1-A to theswitching element Q4. The switching element Q4 is connected by theconductor T1-B to the node N1. The load 120 (see FIG. 11) is connectedto the contact 164, which is connected by the conductor T8-A to theswitching element Q5. The switching element Q5 is connected by theconductor T8-B to a node N8. The node N1 is connected to the node N8 bya conductor T2-A and the node N8 is connected to the capacitor C1 by aconductor T2-B. The remainder of the circuit 500 is substantiallyidentical to the circuit 200 (see FIG. 1). The two switching elements Q4and Q5 are controlled by opposed phases of the clock generator circuit(the first and second trigger signals 170 and 172, respectively). Inthis embodiment, the power source 110 (see FIG. 11) and the load (seeFIG. 11) are always isolated from one another.

Step-Up (Boost) Configuration

Referring to FIGS. 1 and 4-6, each of the circuits 200, 300, 400, and500 has a step-up or boost configuration, which will now be described.The boost configuration may be configured to supply to the load 120 (seeFIG. 11) a mathematical multiplication (e.g., a doubling, a tripling, aquadrupling, and the like) of an input voltage supplied by the powersource 110 (see FIG. 11).

Referring to FIG. 11, the first and second trigger signals 170 and 172may be characterized as having alternating maximum and minimumamplitudes. Because the first trigger signal 170 and the second triggersignal 172 have phases that are offset from one another by 180 degrees,when the first trigger signal 170 is at its maximum amplitude, thesecond trigger signal 172 is at its minimum amplitude, and vice versa.

Referring to FIG. 1, the maximum amplitude of the first trigger signal170 (see FIG. 11) puts a positive voltage in excess of a firstGate-Source threshold voltage (e.g., the first ‘On” threshold) on thegates of the switching elements Q1 and Q3, and places the switchingelements Q1 and Q3 in the conducting, or ‘ON’ states. At the same time,the minimum amplitude of the second trigger signal 172, puts a voltageless than a second Gate-Source threshold voltage (e.g., the second ‘On”threshold) on the gate of the switching element Q2. Thus, the gate ofthe switching element Q2 is held at a voltage below the secondGate-Source threshold voltage, which places the switching element Q2 inthe non-conducting, or ‘OFF’ state. In this first clock-phase state (orthe parallel state), the two capacitors C1 and C2 are connected inparallel, and the voltage of the power source 110 (e.g., a battery) isconnected across both of the capacitors C1 and C2, causing them to becharged to the voltage of the power source 110 (e.g., the battery).

The maximum amplitude of the second trigger signal 172 (see FIG. 11)puts a positive voltage in excess of the second Gate-Source thresholdvoltage on the gate of the switching element Q2, and places theswitching element Q2 in the conducting, or ‘ON’ state. At the same time,the minimum amplitude of the first trigger signal 170, puts a voltageless than the first Gate-Source threshold voltage on the gates of theswitching elements Q1 and Q3. Thus, the gates of the switching elementsQ1 and Q3 are held at a voltage below the first Gate-Source thresholdvoltage, which places the switching elements Q1 and Q3 in thenon-conducting, or ‘OFF’ states. In this second clock-phase state (orthe serial state), the two capacitors C1 and C2 are connected in series.

During the first clock phase state (or the parallel state) as describedabove, the capacitors C1 and C2 are charged in parallel. Thus, thevoltage across each of the capacitors C1 and C2 is equal to the voltageof the power source 110 (see FIG. 11). The frequency and pulse width ofthe first and second trigger signals 170 and 172 and values of thestorage capacitors C1 and C2 are selected so that the current chargetakes the form of a short, high intensity pulse. For example, thecapacitors C1 and C2 may each be a 1 microfarad capacitor when the corecircuit module 220 is tuned for maximum transfer efficiency and thefirst and second trigger signals 170 and 172 are each in the range of 10kHz to 12 kHz.

During the second clock phase state (or the serial state) as describedabove, the storage capacitors C1 and C2 charged during the first clockphase state are now connected in series to the load 120 (see FIG. 11).The voltage across the series-connected pair of capacitors C1 and C2,and therefore available to the load 120, is equal to twice the voltageof the power source 110 (e.g., a battery). This causes the capacitors C1and C2 to discharge into the load 120 with a short, high intensity pulsesimilar in nature to the pulse created when the capacitors C1 and C2were charged.

When the power source 110 is a storage battery (e.g., the battery 130illustrated in FIG. 8), the boost configuration of the circuit 200effectively increases effective storage capacity. Depending upon thefrequency and the pulse width of the first and second trigger signals170 and 172, the circuit 200 may increase output voltage over the entiredischarge cycle. Alternatively, the circuit 200 may be adjusted to givea constant, perhaps even non-boosted output power while the battery 130is in a relatively full state of charge. Then, as battery charge isdepleted, the circuit 200 may continuously be readjusted to boost thediminishing battery voltage and thereby maintain the regulated outputvoltage for a longer period than is possible with conventional circuits.

FIG. 9 illustrates a circuit or system 260. Referring to FIG. 9, if agreater level of boost conversion is required than can be achieved withthe core circuit module 220 (see FIG. 1), one or more circuit modules(e.g., circuit modules CM2 and CM3) may be cascaded from a core circuitmodule CM1 like the core circuit module 220 (see FIG. 1). As shown inFIG. 9, the core circuit module CM1 includes capacitors C5 and C6 andswitching elements Q6-Q8. The circuit module CM2 includes a capacitor C7and switching elements Q9-Q11. The circuit module CM3 includes acapacitor C8 and switching elements Q12-Q14. Thus, each of the cascadedcircuit modules CM2 and CM3 includes a storage capacitor (e.g., thecapacitors C7 and C8, respectively) and three associated switchingelements. However, as may be seen in FIG. 9, the circuit module CM2 issubstantially identical to the core circuit module 220 (see FIG. 1) whenthe capacitor C6 is considered to be an element of the circuit moduleCM2. Similarly, the circuit module CM3 is substantially identical to thecore circuit module 220 (see FIG. 1) when the capacitor C7 is consideredto be an element of the circuit module CM3. The cascaded circuit modulesCM2 and CM3 increase (e.g., double) energy transfer, with actual resultsdepending upon the load 120 that is connected to the system 260.

In the embodiment illustrated, the power source 110 (see FIG. 11) isconnected the contacts 160 and 162 and the load 120 (see FIG. 11) isconnected the contacts 164 and 166. The contacts 160-164 are connectedto the core circuit module CM1 in the same manner the contacts 160-164are connected to the core circuit module 220 (see FIG. 1) of the circuit200 (see FIG. 1). Specifically, the contact 160 is connected to the nodeN1 by the conductor T1, the contact 162 is connected to the node N2 bythe conductor T5, and the contact 164 is connected to the node N4 by theconductor T8. However, unlike in the circuit 200 (see FIG. 1), thecontact 166 is connected by the conductor T14 to a node N9 of the lastcircuit module CM3 (or boost stage). The node N9 is connected betweenthe capacitor C8 and the switching element Q14.

Fifth Embodiment Step-Down (Buck) Configuration

Referring to FIG. 7 operation of a circuit 800 in a step-down or buckconfiguration will now be described. The buck configuration may beconfigured to supply to the load 120 (see FIG. 11) a mathematicaldivision (e.g., one-half, one third, one fourth, and the like) of aninput voltage supplied by the power source 110 (see FIG. 11). Thecircuit 800 may be used to implement the circuit 102 (see FIG. 11). Thepower source 110 (see FIG. 11) is connected to the contacts 160 and 162.The contact 160 is connected by the conductor T1 to the node N1 and thecontact 162 is connected by the conductor T5 to the node N6. The node N1is connected by the conductor T2-A to the node N8. The node N8 isconnected by the conductor T2-B to the capacitor C1. The load 120 (seeFIG. 11) is connected to the contacts 164 and 166. The contact 164 isconnected by the conductor T8 to the node N8 and the contact 166 isconnected by the conductor T14 to the node N4. The remainder of thecircuit 800 is substantially identical to the circuit 200 (see FIG. 1).

Unlike in the other embodiments, in this embodiment, referring to FIG.11, the second trigger signal 172 (see FIG. 11) is delivered to thefirst switching device(s) 152 (e.g., switching elements Q1 and Q3illustrated in FIG. 7) and the first trigger signal 170 (see FIG. 11) isdelivered to the second switching device(s) 154 (e.g., switching elementQ2 illustrated in FIG. 7). Referring to FIG. 7, in operation, themaximum amplitude of the first trigger signal 170 (see FIG. 11) puts apositive voltage in excess of the second Gate-Source threshold voltageon the gate of the switching element Q2, and places the switchingelement Q2 in the conducting, or ‘ON’ state. At the same time, theminimum amplitude of the second trigger signal 172 (see FIG. 11), puts avoltage less than the first Gate-Source threshold voltage on the gatesof the switching elements Q1 and Q3. Thus, the gates of the switchingelements Q1 and Q3 are held at a voltage below the first Gate-Sourcethreshold voltage, placing the switching elements Q1 and Q3 innon-conducting, or ‘OFF’ states. In this first clock-phase state (or theserial state), the two capacitors C1 and C2 are connected in series, andthe voltage of the power source 110 (e.g., the battery) is connectedacross both of the capacitors C1 and C2, causing each of the capacitorsC1 and C2 to be charged to one-half of the voltage of the power source110 (e.g., the battery).

The maximum amplitude of the second trigger signal 172 (see FIG. 11)puts a positive voltage in excess of the first Gate-Source thresholdvoltage on the gates of the switching elements Q1 and Q3, and places theswitching elements Q1 and Q3 in conducting, or ‘ON’ states. At the sametime, the minimum amplitude of the first trigger signal 170, puts avoltage less than a Gate-Source threshold voltage on the gate of theswitching element Q2. Thus, the gate of the switching element Q2 is heldat a voltage below the Gate-Source threshold voltage of the switchingelement Q2, placing it in the non-conducting, or ‘OFF’ state. In thissecond clock-phase state, the two capacitors C1 and C2 are connected inparallel, resulting in a voltage delivered to the load 120 of one-halfof the voltage of the power source 110 (e.g., the battery).

FIG. 10 illustrates a circuit or system 250. Referring to FIG. 10, if agreater level of buck conversion is required than can be achieved withthe circuit 800 (see FIG. 7), one or more circuit modules (e.g., circuitmodules CM5-CM7) may be cascaded from a core circuit module CM4. In theembodiment illustrated, the circuit modules CM4-CM7 each differ from thecore circuit module 220 (see FIG. 1) because the second switchingdevices 154 (see FIG. 11) of the circuit modules CM4-CM7 have beenimplemented as diodes D1-D4 (e.g., Shottky diodes) instead of asswitching elements each like the switching element Q2 (see FIG. 7).

As shown in FIG. 10, the core circuit module CM4 includes capacitors C9and C10, switching elements Q15 and Q16, and the diode D1. The circuitmodule CM5 includes a capacitor C11, switching elements Q17 and Q18, andthe diode D2. The circuit module CM6 includes a capacitor C12, switchingelements Q19 and Q20, and the diode D3. The circuit module CM7 includesa capacitor C13, switching elements Q20 and Q21, and the diode D4. Thus,each of the cascaded circuit modules CM5-CM7 includes a storagecapacitor (e.g., the capacitors C11-C13, respectively), two associatedswitching elements, and a diode. However, as may be seen in FIG. 10, thecircuit module CM5 is substantially identical to the core circuit moduleCM4 when the capacitor C10 is considered to be an element of the circuitmodule CM5. Similarly, the circuit module CM6 is substantially identicalto the core circuit module CM4 when the capacitor C11 is considered tobe an element of the circuit module CM6 and the circuit module CM7 issubstantially identical to the core circuit module CM4 when thecapacitor C12 is considered to be an element of the circuit module CM7.The cascaded circuit modules CM5-CM7 decrease (e.g., by one-half) energytransfer, with actual results depending upon the load 120 that isconnected to the system 260.

In the embodiment illustrated, the power source 110 (see FIG. 11) isconnected the contacts 160 and 162 and the load 120 (see FIG. 11) isconnected the contacts 164 and 166. The contacts 160 and 166 areconnected to the core circuit module CM4 in the same manner the contacts160 and 166 are connected to the core circuit module 220 (see FIG. 7) ofthe circuit 800 (see FIG. 7). Specifically, the contact 160 is connectedto the node N1, and the contact 166 is connected to the node N4.However, unlike in the circuit 800 (see FIG. 7), the contact 164 isconnected to a node N10 of the last circuit module CM7 (or buck stage).The node N10 is connected between the switching element Q21 and a nodeN11. The node N11 is connected between the node 10, the diode D4, andthe capacitor C13. The contact 162 is connected to a node N12 of thelast circuit module CM7 (or buck stage). The node N12 is connectedbetween the capacitor C13 and the switching element Q22.

SIXTH EMBODIMENT Battery Tender Configuration

FIG. 8 is a circuit diagram of a sixth embodiment of a circuit 600 thatmay be used to implement the circuit 102 (see FIG. 11). In the circuit600, the power source 110 (see FIG. 11) is the storage battery 130(e.g., a rechargeable storage battery), connected directly to the corecircuit module 220 as in the first embodiment illustrated in FIG. 1, butwith no load connected. Thus, the circuit 600 is substantially identicalto the circuit 200 (see FIG. 1) except the contacts 164 and 166 (seeFIG. 1) and the conductors T8 and T14 (see FIG. 1) may be omitted.Referring to FIG. 8, the circuit 600 acts as a battery tender orconditioner.

The following sequence of events takes place in the circuit 600,governed, as before, by the two phases of the first and second triggersignals 170 and 172.

The maximum amplitude of the first trigger signal 170 (see FIG. 11) putsa positive voltage in excess of the first Gate-Source threshold voltageon the gates of the switching elements Q1 and Q3, and places theswitching elements Q1 and Q3 in the conducting, or ‘ON’ states. At thesame time, the minimum amplitude of the second trigger signal 172, putsa voltage less than the second Gate-Source threshold voltage on the gateof the switching element Q2. Thus, the gate of the switching element Q2is held at a voltage below the Gate-Source threshold voltage of theswitching element Q2, placing it in the non-conducting, or ‘OFF’ state.In this first clock-phase state (or parallel-capacitor charging state),the two capacitors C1 and C2 are connected in parallel, and the voltageof the power source 110 (e.g., the battery 130) is connected across bothof the capacitors C1 and C2, causing them to be charged to the voltageof the power source 110.

The maximum amplitude of the second trigger signal 172 (see FIG. 11)puts a positive voltage in excess of the second Gate-Source thresholdvoltage on the gate of the switching element Q2, and places theswitching element Q2 in the conducting, or ‘ON’ state. At the same time,the minimum amplitude of the first trigger signal 170, puts a voltageless than the first Gate-Source threshold voltage on the gates of theswitching elements Q1 and Q3. Thus, the gates of the switching elementsQ1 and Q3 are held at a voltage below the first Gate-Source thresholdvoltage, placing them in non-conducting, or ‘OFF’ states. In this secondclock-phase state (or series-capacitor discharge state), the twocapacitors C1 and C2 are connected in series.

With input and output nodes connected together in the circuit 600,current pulses drawn from the power source 110 (e.g., the battery 130)during the parallel-capacitor charging state and voltage-boosted pulsesgenerated during the series-capacitor discharge state are both deliveredto the power source 110 (e.g., the battery 130). If the current flow isobserved using an oscilloscope and an appropriate current probe, it willbe seen that during the parallel-capacitor charging state, current isdrawn from the power source 110 in short, high-current pulses. On theother hand, during the series-capacitor discharge state, current pulsesvery similar in nature to those seen during the parallel-capacitorcharging state will be observed moving in opposite polarity, sendingcurrent back to the power source 110. Thus, the circuit 600 both drawscurrent from, and injects current into, the power source 110 (e.g., thebattery 130), in a pulse form.

If the storage battery 130 is used as the power source 110 (see FIG.11), this configuration is effective in countering the effects ofbattery self-discharge, and also works to counter the long term effectsof neglecting to keep a battery in a charged state. To use a lead acidautomotive starting battery as an example, open-circuit battery voltageself-discharge occurs at a rate of 3 percent per month to 20 percent permonth, the actual value dependent upon storage temperature and otherfactors. Additionally, lead-acid batteries suffer from a condition knownas sulfation. When lead-acid batteries are not properly and regularlycharged, lead sulfate crystals build up on the negative plate,effectively reducing the surface area of the battery plate and therebyreducing battery capacity.

A compact, two-wire device can be manufactured in accord with thecircuit 600, such that it can be mounted permanently to a singleautomotive lead-acid battery. The net power consumption of the circuit600 is extremely low. Further, significant discharge-current pulses andcharge-current pulses are observed in the current domain, such that anet sum of the opposing, and temporally-isolated, pulses is near zero.

Using fast, high current pulses to break up sulfation on a negativeplate of a lead-acid battery is a technique well understood by those ofordinary skill in the art, and the principle is used in a number ofcommercially-available battery charger designs. But, every commercialimplementation of pulsed anti-sulfation requires input of significantpower in order to supply the energy applied in the form of pulsation. Itis not necessary to inject additional power into the circuit 600,because the circuit 600 stores the battery's own energy, and feeds thatenergy back to the battery in pulses that effectively remedy thesulfation condition.

These same pulses feed back into the storage structure of a healthybattery, maintaining a baseline charge when the battery is not supplyingpower to the load 120, effectively reducing self-discharge rates. Whenthe load 120 (see FIG. 11) is connected, the circuit 600 remainsessentially invisible to the transfer of energy from the battery to theload 120.

Referring to FIGS. 1 and 4-10, each of the embodiments described aboveincludes the core circuit module 220 (or the core circuit module CM1 inFIG. 10) that is connectable to the power source 110 (see FIG. 11) and,in some instances, the load 120 (see FIG. 11). The circuits 102, 200,260, and 300-800 may be characterized as being synchronous,switched-capacitor power controllers. The components of the circuits102, 200, 260, and 300-800 are non-inductive and non-magnetic. The corecircuit module 220 includes the two capacitors C1 and C2, connectedtogether within a switching matrix that includes switching elementsQ1-Q3, plus any necessary supporting components (e.g., the nodes N1-N6and at least some of the conductors T1-T16). The switching elementsQ1-Q3 may be implemented as three N-Type power MOSFETs or similar powerswitching circuit elements. It will be understood by those of ordinaryskill in the art, as shown in FIG. 10, that multiples of the corecircuit module 220 (see FIG. 1) may be connected in a cascade fashion ifincreased power and/or voltage levels are desired. Referring to FIGS. 1and 4-10, when operating, the circuits 102, 200, 260, and 300-800alternate between series and parallel connections of capacitive elements(e.g., the capacitors C1 and C2 or the capacitors C5-C8). Referring toFIG. 11, the alternating nature of this connection is established by thedrive circuit(s) 104 and the pulse generating circuit(s) 106 (which maybe implemented as a two-phase clock circuit). The first and secondtrigger signals 170 and 172 function as controlling waveforms thatcontrol the switching elements (e.g., the switching elements Q1-Q14) inthe circuits 102, 200, 260, and 300-800.

The foregoing described embodiments depict different componentscontained within, or connected with, different other components. It isto be understood that such depicted architectures are merely exemplary,and that in fact many other architectures can be implemented whichachieve the same functionality. In a conceptual sense, any arrangementof components to achieve the same functionality is effectively“associated” such that the desired functionality is achieved. Hence, anytwo components herein combined to achieve a particular functionality canbe seen as “associated with” each other such that the desiredfunctionality is achieved, irrespective of architectures or intermedialcomponents. Likewise, any two components so associated can also beviewed as being “operably connected,” or “operably coupled,” to eachother to achieve the desired functionality.

While particular embodiments of the present invention have been shownand described, it will be obvious to those skilled in the art that,based upon the teachings herein, changes and modifications may be madewithout departing from this invention and its broader aspects and,therefore, the appended claims are to encompass within their scope allsuch changes and modifications as are within the true spirit and scopeof this invention. Furthermore, it is to be understood that theinvention is solely defined by the appended claims. It will beunderstood by those within the art that, in general, terms used herein,and especially in the appended claims (e.g., bodies of the appendedclaims) are generally intended as “open” terms (e.g., the term“including” should be interpreted as “including but not limited to,” theterm “having” should be interpreted as “having at least,” the term“includes” should be interpreted as “includes but is not limited to,”etc.). It will be further understood by those within the art that if aspecific number of an introduced claim recitation is intended, such anintent will be explicitly recited in the claim, and in the absence ofsuch recitation no such intent is present. For example, as an aid tounderstanding, the following appended claims may contain usage of theintroductory phrases “at least one” and “one or more” to introduce claimrecitations. However, the use of such phrases should not be construed toimply that the introduction of a claim recitation by the indefinitearticles “a” or “an” limits any particular claim containing suchintroduced claim recitation to inventions containing only one suchrecitation, even when the same claim includes the introductory phrases“one or more” or “at least one” and indefinite articles such as “a” or“an” (e.g., “a” and/or “an” should typically be interpreted to mean “atleast one” or “one or more”); the same holds true for the use ofdefinite articles used to introduce claim recitations. In addition, evenif a specific number of an introduced claim recitation is explicitlyrecited, those skilled in the art will recognize that such recitationshould typically be interpreted to mean at least the recited number(e.g., the bare recitation of “two recitations,” without othermodifiers, typically means at least two recitations, or two or morerecitations).

Accordingly, the invention is not limited except as by the appendedclaims.

1. An electrical power conversion apparatus comprising: a plurality ofenergy storage devices; a plurality of switching devices connected tothe plurality of energy storage devices, the plurality of switchingdevices comprising at least one first switching device and at least onesecond switching device, the plurality of switching devices beingarranged to connect the plurality of energy storage devices in parallelwhen the plurality of switching devices are in a first state in whichthe at least one first switching device is conducting electrical currentand the at least one second switching device is not conductingelectrical current, the plurality of switching devices being arranged toconnect the plurality of energy storage devices in series when theplurality of switching devices are in a second state in which the atleast one first switching device is not conducting electrical currentand the at least one second switching device is conducting electricalcurrent; and at least one drive circuit connected to the plurality ofswitching devices, the at least one drive circuit providing triggersignals to the plurality of switching devices when the apparatus isoperating, the trigger signals alternately placing the plurality ofswitching devices in the first state and in the second state.
 2. Theapparatus of claim 1 for use with a power source, a pulse generatingcircuit connected to the at least one drive circuit, the trigger signalsbeing electrically isolated from the pulse generating circuit by the atleast one drive circuit, the pulse generating circuit deliveringsynchronized first and second clock signals to the at least one drivecircuit when the apparatus is operating, the at least one drive circuitgenerating the trigger signals based on the first and second clocksignals when the apparatus is operating, the pulse generating circuitreceiving power from the power source when the apparatus is operating,the power source providing a substantially constant voltage to the pulsegenerating circuit when the apparatus is operating.
 3. The apparatus ofclaim 1, wherein one or more of the plurality of switching devices arebipolar transistors or metal oxide field effect transistors.
 4. Theapparatus of claim 1, wherein the at least one first switching devicecomprises first and third switching devices, the at least one secondswitching device comprises a second switching device, the plurality ofenergy storage devices comprise a first capacitor and a secondcapacitor, the first switching device is electrically connected to thefirst capacitor and the second switching device, the third switchingdevice is electrically connected to the second capacitor and the secondswitching device, the second switching device is electrically connectedbetween the first capacitor and the third switching device, and thesecond switching device is electrically connected between the firstswitching device and the second capacitor.
 5. The apparatus of claim 4for use with a power source and a load, the power source providing aninput voltage, wherein the power source is connectable to the apparatusacross the first capacitor, the load is connectable to the apparatusacross the third switching device, and the first and second capacitorsare connected in parallel to the power source when the plurality ofswitching devices are in the first state, and the first and secondcapacitors are connected in series to the load when the plurality ofswitching devices are in the second state to thereby create amathematical multiplication of the input voltage and cause the apparatusto act as a voltage boost converter.
 6. The apparatus of claim 4 for usewith a rechargeable storage battery, wherein the rechargeable storagebattery is connectable to the apparatus across the first capacitor, andthe first and second capacitors are connected in parallel to therechargeable storage battery when the plurality of switching devices arein the first state, and the first and second capacitors are connected inseries when the plurality of switching devices are in the second stateto thereby cause the apparatus to both draw current from, and injectcurrent into, the rechargeable storage battery, in a pulse form.
 7. Theapparatus of claim 4 for use with a power source and a load, the powersource providing an input voltage, wherein the power source isconnectable to the apparatus across the first capacitor, the load isconnectable to the apparatus across the third switching device, thefirst and second capacitors are connected in series to the power sourcewhen the plurality of switching devices are in the second state, and thefirst and second capacitors are connected in parallel to the load whenthe plurality of switching devices are in the first state to therebycreate a mathematical division of the input voltage at the load.
 8. Theapparatus of claim 7, further comprising: electrical components arrangedto provide increased electrical isolation between the plurality ofswitching devices and at least one of the power source and the load. 9.The apparatus of claim 1, further comprising: a pulse generating circuitconnected to the at least one drive circuit, the trigger signals beingelectrically isolated from the pulse generating circuit by the at leastone drive circuit, the pulse generating circuit delivering synchronizedfirst and second clock signals to the at least one drive circuit whenthe apparatus is operating, the at least one drive circuit generatingthe trigger signals based on the first and second clock signals when theapparatus is operating, the first clock signal comprising first timingpulses having a first phase, the second clock signal comprising secondtiming pulses having a second phase, the first and second phases being180 degrees out of phase from another.
 10. The apparatus of claim 9,wherein the pulse generating circuit has a digital single-to-bi-phaseconverter that generates the first and second clock signals, and each ofthe first and second clock signals have a constant 50 percent dutycycle.
 11. The apparatus of claim 10, wherein the first timing pulsesare varied continuously over a range of approximately 100 Hz toapproximately 100 kHz, and the second timing pulses are variedcontinuously over the range of approximately 100 Hz to approximately 100kHz.
 12. The apparatus of claim 9, wherein the first timing pulses havea first pulse width, the second timing pulses have a second pulse width,the pulse generating circuit has an digital timing circuit thatgenerates the first and second clock signals in a push-pull timingconfiguration in which the first pulse width is equal to the secondpulse width.
 13. The apparatus of claim 12, wherein the digital timingcircuit is configured to vary an operating frequency of the pulsegenerating circuit over a range of approximately 100 Hz to approximately500 kHz, and to vary the first and second pulse widths over a duty cyclehaving a range from approximately 1 percent to approximately 100percent.
 14. The apparatus of claim 12, wherein the pulse generatingcircuit has an operating frequency, and the operating frequency and thefirst and second pulse widths are varied by a digital communicationsprotocol.
 15. The apparatus of claim 14, wherein the digitalcommunications protocol is RS-232 serial or Bluetooth protocol.
 16. Theapparatus of claim 1, wherein the trigger signals comprise a firsttrigger signal and a second trigger signal, the first and second triggersignals have an operating frequency; the first trigger signal comprisesfirst pulses having a first pulse width, the second trigger signalcomprises second pulses having a second pulse width, and the apparatusfurther comprises one or more digital encoders configured to vary theoperating frequency and the first and second pulse widths.
 17. Theapparatus of claim 1, wherein the trigger signals comprise a firsttrigger signal and a second trigger signal, the first and second triggersignals have an operating frequency; the first trigger signal comprisesfirst pulses having a first pulse width, the second trigger signalcomprises second pulses having a second pulse width, and the apparatusfurther comprises an electrical device connected to the at least onedrive circuit, the electrical device delivering synchronized first andsecond signals to the at least one drive circuit when the apparatus isoperating, the at least one drive circuit generating the first andsecond trigger signals based on the first and second signals,respectively, when the apparatus is operating, the operating frequencyand the first and second pulse widths having been determined by theelectrical device.
 18. The apparatus of claim 1, further comprising: apulse generating circuit connected to the at least one drive circuit,the pulse generating circuit delivering clock signals to the at leastone drive circuit when the apparatus is operating, the at least onedrive circuit generating the trigger signals based on the clock signals.19. The apparatus of claim 1, wherein the plurality of energy storagedevices are capacitors or batteries.
 20. An electrical power conversionapparatus comprising: at least one first drive circuit; at least onesecond drive circuit; at least one first switching device connected tothe at least one first drive circuit, the at least one first drivecircuit being configured to provide a first trigger signal to each ofthe at least one first switching device, the first trigger signalindicating whether the at least one first switching device is in aconducting state or a non-conducting state; at least one secondswitching device connected to the at least one second drive circuit, theat least one second drive circuit being configured to provide a secondtrigger signal to each of the at least one second switching device, thesecond trigger signal indicating whether the at least one secondswitching device is in a conducting state or a non-conducting state, thesecond trigger signal being offset from the first trigger signal suchthat the at least one second switching device is in the conducting statewhen the at least one first switching device is in the non-conductingstate, and vice versa; and a plurality of energy storage devicesconnected to the at least one first switching device and the at leastone second switching device, the plurality of energy storage devicesbeing connected in parallel when the at least one first switching deviceis in the conducting state and the at least one second switching deviceis in the non-conducting state, the plurality of energy storage devicesbeing connected in series when the at least one first switching deviceis in the non-conducting state and the at least one second switchingdevice is in the conducting state.
 21. The apparatus of claim 20,further comprising: a pulse generating circuit isolated from the atleast one first switching device by the at least one first drive circuitand isolated from the at least one second switching device by the atleast one second drive circuit, the at least one first drive circuitreceiving a first signal from the pulse generating circuit and producingthe first trigger signal based thereupon when the apparatus isoperating, the at least one second drive circuit receiving a secondsignal from the pulse generating circuit and producing the secondtrigger signal based thereupon when the apparatus is operating.
 22. Theapparatus of claim 21, wherein the first signal determines a frequencyand a pulse width of the first trigger signal and the second signaldetermines a frequency and a pulse width of the second trigger signal.23. The apparatus of claim 20 connected to a load and a power source andfunctioning as a voltage boost converter, wherein the plurality ofenergy storage devices are connected to the power source when theplurality of energy storage devices are connected in parallel, theplurality of energy storage devices are connected to the load when theplurality of energy storage devices are connected in series, alternatingbetween a parallel connection and a series connection increasing aninput voltage received from the power source and supplied to the load.24. The apparatus of claim 20 connected to a rechargeable storagebattery, wherein the plurality of energy storage devices are connectedto the rechargeable storage battery when the plurality of energy storagedevices are connected in parallel and series, and alternating between aparallel connection and a series connection both draws current aselectronic pulses from the rechargeable storage battery, and injectscurrent as electronic pulses into the rechargeable storage battery. 25.The apparatus of claim 20 connected to a load and a power source,wherein the plurality of energy storage devices are connected to thepower source when the plurality of energy storage devices are connectedin series, the plurality of energy storage devices are connected to theload when the plurality of energy storage devices are connected inparallel, alternating between a parallel connection and a seriesconnection decreasing an input voltage received from the power sourceand supplied to the load.